Method and apparatus for the examination of the internal interconnection system between n terminals of an electrical network

ABSTRACT

A method for the examination of an internal interconnection system between n terminals of an electrical network and for storing the results in a memory comprising n memory cells by means of measuring the existence or non-existence of the signal passage between the terminals, in which a demultiplexer is used to pass a marking state on a terminal of the network and a multiplexer is used to detect the throughpass of the marking signal to other terminals of the network in first cycles a, and when such passage is detected, the positions of the demultiplexer and the multiplexer are stored together with a so called closing bit representing the end of a series of interconnections, and in subsequent cycles b the next undetected terminal is determined which is followed by a next cycle a, and this sequence is continued until all interconnections of the network get stored in the memory. In the apparatus for carrying out the method a first address generator (DMC) is associated with the demultiplexer (DMPX) and a second one (MPC) with the multiplexer (MPX), and a memory (MEM) is used to set the multiplexer. The setting of the multiplexer is temporarily stored in a register (REG) which is subsequently read in the memory. The memory sets the demultiplexer to the selected terminals. The memory setting is facilitated by a memory addressing circuit (MEC). The apparatus is designed to function in accordance with the method and comprises a pair of comparators storing threshold values used for the logical minimizing operations defining the actual fresh memory addresses.

The invention relates to a method for the examination of the internalinterconnection system between n terminals of an electrical network andfor storing the results of examination in a memory with n memory cellsby means of measuring the existence or non-existence of signal passagebetween the terminals. The invention relates also to a method which cantest an electrical network manufactured as a reproduction of a standardelectrical network which has an interconnection system already examinedand stored in a memory, such test including the indication of thedifferences between the tested and the standard networks. The inventionrelates to an apparatus for carrying out both kinds of method.

As it is widely known in the art in the field of manufacturingelectrical networks with a large number of terminals the examination orcontrol test of the interconnection system between the terminals is ofoutstanding significance.

In making such examinations information of "yes" or "no" type isrequired indicating whether there exists a connection between a testedpair of terminals or it is not existing. In general, the existence of aconnection can be established if the electrical resistance between theterminals is below a threshold limit, and there is no connection, if theresistance is higher than the threshold limit.

Especialy in case of networks with large number of terminals (such asexceeding a couple of hundred or thousand terminals) the performance ofsuch examinations is rather complicated and requires the usage of highlyexpensive machinery. The degree of complexity increases excessively withthe number of terminals and the equipments designed for operating withsmaller number of terminals can not be expanded due to theoreticalconsiderations, because extending the number of terminals, certaininevitable additional problems will emerge. The main problem lies inthat in the electrical network in principle an unlimited proportion ofterminals can be galvanically interconnected to form a common point, andamong the testing circuits connected to these terminals unwantedcouplings and interactions might take place.

For the examination of networks with a large number of terminalscomputers are used due to the excessively large number of possiblecombinations, and the data defining the respective status conditions arestored in the memory of the computer. As far as we are informed, therehave not been published any electronic means with self-programmingperformance which could automatically examine the internal structure ofinterconnections of an unknown electrical network.

The object of the invention is to provide a method and an apparatus forthe examination and test of the internal interconnection system of anelectrical network with a plurality of terminals which is capable ofinvestigating the structure of interconnections of an unknown network bymeans of self-programming steps, which does not require complicatedprocessor operations or even the usage of a processor and which has aminimized need for storage capacity that does not exceed the number ofterminals of the network, i.e. in which the stored information has aminimum redundancy.

In a first aspect of the invention a method has been provided for theexamination of an internal interconnection system between n terminals ofan electrical network and for storing the results in a memory comprisingn memory cells by means of measuring the existence or non-existence ofthe signal passage between the terminals, in which according to theinvention the method comprises the steps of switching a marking state onthe respective terminals by means of a demultiplexer with n outputscontrolled by an address generator and searching the passage of themarking state by a multiplexer with n inputs connected to the terminalsand being set by an other address generator, and in each stable state ofthe demultiplexer the throughpass of the marking state being searchedaccording to steps of first cycles designated as cycles A, in each ofsaid cycles A said multiplexer is stepped from the terminal associatedwith said stable state of the demultiplexer till the last terminal, andin each step watching the state of the multiplexer output and if in thatoutput an active state representing the throughpass of said markingstate is detected, the actual address of the multiplexer is temporarilystored and when the next active state in said output is detected, thetemporarily stored address is written in the momentarily addressed cellof the memory together with a closing bit having a first logical valueassociated with said active state, whereafter the next address of thememory is set and the momentary multiplexer address is storedtemporarily, and this repeated sequence of steps is continued until themultiplexer is connected to the n-th, last terminal, and in the nextstep the temporarily stored address is written in the next free addressof the memory together with a closing bit having a second logical valueinverted relative to said first logical value and stepping the memory tothe next address, then starting a second B-type cycle for adjusting thenext stable state of the demultiplexer, in which the demultiplexeraddress is increased by respective steps and in each step this addressis compared with the contents of the already filled memory cells and ifidentity is found, the demultiplexer address is increased by a step andthis increased step is compared to the content of the already writtenmemory cells beginning with the first cell, and if neither of thecontents of the filled memory cells is found to coincide the actualdemultiplexer address, then this latter is accepted as a stabledemultiplexer address, then starting a further cycle A, and by means ofthe alternating series of the cycles A and B all the n cell of thememory being written in.

According an other aspect of the invention a method has been providedfor testing the identity of an internal interconnection systeminterpreted among terminals of a network with that of a standardnetwork, in which the internal interconnection of the standard networkis recorded in a memory according to the above described method andaccording to the invention this method is characterized by the steps ofswitching a marking state on the respective terminals of the networkunder test by means of a demultiplexer addressed by an addressgenerator, and by means of a multiplexer with inputs connected to saidterminals and addressed by a second address generator, the arrival ofthe marking state to the multiplexer output is tested as a proof ofshort-circuit or as a continuty test between the actually connectedterminals, and the short-circuit and continuity test examinations arecarried out in alternating cycles, and in the short circuit controlcycles the demultiplexer is set to addresses for which is true that inthe memory cell with the same address the value of the closing bitcorresponds to said second logical value, and during maintaining suchdemultiplexer states the memory address is increased by steps and ineach step the memory content is read, and when the read value of theclosing bit corresponds to said second logical value, then themultiplexer is set to the address stored in the same memory cell and theoutput state there of is examined, and if in this output the markingstate that is a short-circuit is detected, then an error indication ismade, following the end of each of said first cycles the memory cellwith the next address is read and the demultiplexer is set to theposition corresponding to the number stored in this cell, and if thevalue of the closing bit stored in this cell takes the second logicalvalue, then an other short-circuit test cycle is started, and if theclosing bit has the other i.e. first logical value, then a second typecontinuity test cycle is started, in which the multiplexer is set to theposition determined by the number stored in the memory cell with thenext address, and the state of the multiplexer output is detected, andif the lack of marking state i.e. continuity is measured, an errorindication is made, and if continuity is detected, then thedemultiplexer is set to the position defined by the number stored in thememory cell with said next address and depending on the value of theclosing bit stored in this cell a further short-circuit or continuitytest cycle is started.

In a preferable embodiment of this method the tests are carried out in arange defined between two predetermined limit memory addresses, in whichthe demultiplexer is set first to the position stored in one of saidlimit addresses, and the type of the first cycle is defined by thelogical value of the closing bit in this address.

According to a further aspect of the invention an apparatus has beenprovided by which both the examination and control test methods can becarried out and this apparatus comprises a demultiplexer with outputsconnected to the n terminal of the network under test, a multiplexerwith inputs connected to said terminals, a first address generatorconnected to address input of the demultiplexer, a second addressgenerator connected to address input of the multiplexer, a registerconnected to the output of the multiplexer for temporarily storing thevalue of this output, a selector which can be set according to therequired mode of operation and which has an output connected to addressinput of the second address generator, a first input connected to theoutput of the first address generator, a memory comprising n cells whichhas data inputs connected with one exception to the outputs of theregister, the data output of the memory are connected with one exceptionto the address input of the first address generator and to second inputof the selector, a memory addressing circuit coupled to the addressinputs of the memory, a means for determining the identity of the memorycontent and the actual position of the first address generator, a meansfor temporary storage of given states of the memory addressing circuitand for indicating the fact when the memory addressing circuit takessaid states again and a control unit which receives the output of themultiplexer, the remaining one data output of the memory, the output ofthe means for determining the identity, the output of the temporarystorage means, said control unit comprises control outputs for settingthe remaining one data input of the memory and for controlling the firstand second address generators, the selector, the register, the memoryaddressing circuit and the memory.

The method according to the invention both during performance ofexamination and test tasks takes the information, obtained about thenetwork earlier, into consideration, therefore the number of examiningsteps is minimized and the number of memory cells required for storingthe results of examination will also be at minimum. Owing to the usageof the closing bit the internal structure of the network is stored inthe consecutive memory addresses in logical groups in such a way that ina group the closing bit of the interconnected terminals has a logical"1" value till the last number of the group which has a logical "0"value. Such way of information storage facilitates the identification ofthe erroneous connections and the search.

The invention will now be described in connection with examplaryembodiments thereof, in which reference will be made to the accompanyingdrawings. In the drawing:

FIG. 1 shows the general block diagram of the apparatus according to theinvention,

FIG. 2 shows a detail from a portion of the network to be tested, and

FIG. 3 visualizes the filling of the memory in table form.

FIG. 1 shows an electrical network NW which comprises "n" terminals. Inthe network the terminals are interconnected according to an internalstructure corresponding to the task and function of the network NW.These interconnections are of "yes" or "no" type, and the value of anyparticular connection can be established on the basis of the electricalresistance measured between the corresponding terminals i.e. whetherthis resistance is beyond or below a predetermined threshold level. Thestructure of internal interconnections among the "n" terminals can beunknown, and in that case the task lies in the examination and thestorage of the examined structure, or this structure can be alreadyknown and available in a stored form, and in that case the task lies inthe control of the actual structure of interconnections of a testednetwork whether it fully corresponds to the stored predeterminedstructure. The performance of these two tasks requires basicallydifferring implementations. In the following description the first taskwill be referred to shortly as "examination" and the second one as"control" or "tests". The value of "n" can be as high as several hundredor even several thousand or tens of thousand. From this high number itwill be clear that the accomplishment of these tasks can not be toosimple.

In FIG. 1 its is shown that the terminals of the network NW areconnected to number n outputs of a demultiplexer DMPX and to number ninputs of a multiplexer MPX. The actual state of the demultiplexer DMPSis defined by address generator DMC and that of the multiplexer MPX isdefined by address generator MPC. The address generator MPC has a datainput 12 and a control input 20. The demultiplexer DMPX supplies aground potential to the output addressed by the address generator MPC,while the electrical state of the output V of the multiplexer MPX ishigh or low depending on the electrical state of the path resistancebetween the addressed multiplexer input towards the ground i.e. whetherthis path is closed or broken.

The actual state of the address generator DMC is defined by the signalspresent in its data input 10 and control input 11 (such as shifting,writing or clearing inputs). The address delivered at the output of theaddress generator DMC is coupled not only to the address input of thedemultiplexer DMPX but also to first input of a first comparator KOM 1and to an input of selector SEL. The output of the selector SEL isconnected to the data input of the address generator MPC, and the actualposition of the selector SEL is defined by the control coupled to modecontrol input 19 thereof.

The apparatus comprises a memory MEM with number n addressable memorycells with data inputs connected with one exception through line 15 tooutput of register REG and the remaining one input is connected throughline 13 to control unit CU for the storage of a closing bit 2 (to beexplained later). The data inputs of the register REG are connected tothe output of the address generator MPC, and the control input 18 of theregister REG is connected to the control unit CU.

Address inputs 16 of the memory MEM are connected to output of memoryaddressing circuit MEM having an input coupled to output of a secondcounter CNT 2 and to an input of second comparator KOM 2. The otherinput of the second comparator KOM 2 is connected to output of firstcounter CNT 1. The first counter CNT 1 is controlled as it will bedescribed later together with the memory addressing circuit MEC andstores the state of the memory addressing circuit MEC when this lattershould be stepped during a sub-cycle. The data outputs of the memoryMEM--with the exception of the output corresponding to the closingbit--are connected through line 14 to the data input 10 of the addressgenerator DMC, to the second input of the first comparator KCM 1 and tosecond input of the selector SEL. The data output of the closing bit isconnected through line 17 to the control unit CU. The outputs of bothcomparators KOM 1 and KOM 2 and the output V are connected to respectiveterminals of the control unit CU.

The task of the control unit CU is the coordination of the operation ofthe whole apparatus and for that reason the control unit CU is connectedto the writing, shifting, clearing and enable i.e. in general controlinputs of all functional units of the apparatus and to the mode controlinput 19 of the selector SEL. The control unit CU can be implemented bya sequential logical circuit or by a processor controlled unit, however,the structural design of the control unit CU can be less complicated ifthe functional units such as the address generators DMC and MPC, thememory addressing circuit MEC and the register REG are designed for highperformance control i.e. if these units have writing, stepping,shifting, reset etc. properties. The memory MEM receives the controlsignals required for its normal operation also from the control unit CU.For the sake of preserving transparency of FIG. 1 the connectionsbetween certain outputs and inputs of the functional units and thecontrol units have been symbolized by identical reference numbersinstead of interconnecting lines.

The operation of the appratus according to the invention and theimplementation of the method will be described in connection withsolving exemplary tasks.

When a network NW with unknown internal structure is examined, the tasklies in the establishment of the internal structure between theterminals and in the storage of the established structure in a memory.If in case of a network of a given type the internal structure hasalready been established, then in case of other manufactured similarnetworks should be checked or controlled whether their internalstructure actually correspond to the stored one which can be consideredas a gauge. During performance of this latter task the discrepanciesbetween the tested network and the original one should be recorded indetail.

In accordance with the two different tasks the apparatus according tothe invention has two different modes of operation referred to as"examination" and "control" modes, respectively, and the method can alsobe divided in similar two cathegories. In examination mode the selectorSEL couples the data output of the address generator DMC to the datainput 12 of the address generator MPC, while in the control mode thedata output of the memory MEM is coupled to the data input 12. The wayof operation of the control unit CU depends also on the actual mode.

First the examination mode will be described, and the task ofexamination lies in the establishment of the internal structure of anetwork shown in FIG. 2, in which the terminals 1 and 3, as well as 2, 4and 5 are interconnected. The table of FIG. 3 contains the correspondingdata of the address register DMC, the memory addressing circuit MEC andthe content of the addressed memory cell which can be divided into DATAand closing bit Z. portions.

For the case of further simplification the content of certain unitsshown in FIG. 1 will be referred to by means of the letter combinationlabels associated with such units.

In the beginning DMC=0 which means that the demultiplexer DMPX connectsa ground potential to the 0th terminal. In that case the conditionDMC=MPC=0 will be set through the selector SEL, and the 0-th input ofthe multiplexer MPX obtains a passage to the multiplexer output. As aconsequence of the ground potential switched on the 0-th terminal, thelogical state of the output V will be "1". In this beginning state theMPC=DMC value will be written in the register REG.

The DMC=0 condition will then be maintained, and the value of theaddress generator MPC will be increased one by one by means of thecontrol unit CU, and in each step when the multiplexer MPX connects theappropriate input to its own output, the actual value of the output V isdetected. If V=0 is detected, the address generator MPC will be steppedforward. This is clear, because if V=0 is experienced, then there is nointernal connection between the terminal associated with the ectuallyenabled multiplexer input and the 0-th terminal grounded by thedemultiplexer DMPX. In the example of FIG. 2 the 0-th terminal is notconnected to any other terminals, therefore the address generator MPCsteps forward through n steps and during that time the multiplexer MPXenables the detection of the state of each terminal. When the n-thcondition is reached, the following events take place:

a logical level "1" is coupled to the line 13 by the control unit CU,

the number stored in the register REG is written in the DATA field ofthe actually addressed cell of the memory MEM. During this writingoperation the value "1" will be written in the memory as closing bitZ=1.

Now the memory addressing circuit MEC is in the 0-th condition (MEC=0)and the writing occurs in the 0-th memory cell. When the writingoperation is finished, the memory address will be increased by 1, i.e.MEC=1 is obtained. By this step the examination of the 0-th terminal isfinished. Similar examinations will be cyclically repeated in case ofthe subseqeunt terminals, and such cycles will be referred to as cyclesA. In the following step the setting of the address generator DMC takesplace. In the present example this means the simple increase of theprevious value DMC=0 by 1, i.e. DMC=1 will be set, whereby the groundpotential is switched on the first terminal on the network NW. Thesetting of the address generator DMC takes place in separate cyclesreferred to as cycles B.

When the demultiplexer DMPX has been set to DMC=1, the stepping of themultiplexer MPX takes place which occurs in a further cycle A. In thesecond cycle A the DMC=MPC value will first be set, which is now equalto 1. The setting of the multiplexer MPX to a value smaller then DMC isunnecessary, since in the previous cycle the connection between the 0-thand first terminals has already been examined.

When the MPC=1 is set, the ground potential of DMC=1 occurs at themultiplexer output V, and the value of the address generator MCP (now 1)is written again in the register REG. This is followed by the steppingof the address generator MPC one by one, and the state of the output Vis watched. In case of MPC=2, V=0 is obtained because in the secondinput the path towards the ground is broken. In the third terminal,however, when MPC=3, V=1 is detected, which indicates that the thirdterminal is connected with the first one. In that case the followingevents take place:

the content of the register REG is written in the memory MEM in theaddress MEC=1, and the memory addressing circuit MEC is stepped forwardand MEC=2 is obtained. During the writing operation the control unit CUconnects the output V with the line 13, therefore the value of theclosing it will be Z=1;

thereafter the value MPC=3 is written in the register REG and theaddress generator MPC is stepped forward one by one. If no furtherlogical value "1" is detected, then in case of reaching the n-thterminal, the already described events will be repeated, i.e. theregister value (number 3) together with the value "0" connected to theline 13 as a closing bit will be written in the actually addressed(MEC=2) memory cell and the memory address is increased, i.e. MEC=3 isobtained.

This means the end of this cycle A, and the next cycle B can be started.

In this cycle B the demultiplexer address is increased by one, i.e.DMC=2 is set, and the ground potential is connected to the secondterminal, furthermore the DMC=MPC=2 condition is set. By this conditionthe cycle B is finished and a further cycle A is started.

In this cycle A the MPC=2 value is written in the register REG, and themultiplexer MPX steps forward beginning from the second position and thevalue of the output V is watched. While the second terminal isinterconnected with the fourth terminal, when the MPC=4 condition isset, V=1 is obtained. Consequently the memory operations characteristicto the cycle A will be repeated, i.e.:

the content of the register REG together with the V=Z=1 value will bewritten in the actually adressed (MEC=3) cell of the memory MEM. Thememory address is increased by one (MEC=4).

the actual MPC=4 value is written in the register REG. Following thiswriting sub-cycle, the multiplexer address is increased by one (MPC=5),and now again V=1 is detected, thus a further writing sub-cycle isstarted, in which the value MPC=4 stored in the register REG is writtenin the address MEC=4 together with the closing bit Z=1, the memoryaddress is increased by one (MEC=5 is obtained), and the value MPC=5 iswritten in the register REG.

In the further steps of the multiplexer MPX the V=1 value will not beobtained any more, and upon reaching the n-th terminal, the closingsub-cycle is repeated, i.e. the value MPC=5 stored in the register REGand the closing bit "0" sent to the line 13 will be written in theaddress MEC=5, the memory address is increased (MEC=6 is obtained) andthe cycle A is finished.

This will be followed by an other cycle B. The full logical conditionsystem of building the cycle B can be explained only now.

In the beginning the value of the address generator DMC will beincreased by one. Now DMC=3 is obtained. Looking at FIG. 2 it can beseen that in case of DMC=3 the ground potential is switched on theterminal 3 of the network NW. In this position the measurements becomeunnecessary, since the interconnection of the first and third terminalshas already been detected, and in case of DMC=1 all possible connectionsof the first terminal were examined. This explains that the examinationshould not be repeated with DMC=3, because such examination would notgive any new information, would require superfluous memory space and itwould reduce the overall view on the stored data. The condition DMC=3will therefore not be set, and the next value DMC=4 is adjusted. In thiscondition there is again no worth making an examination because this wasalready done in connection with terminal 2, therefore the DMC=4 can alsobe stepped over. A similar situation is obtained in the next DMC value,i.e. when DMC=5 because this is also identical with the situationobtained when DMC=2 was set. The next stable step for the addressgenerator DMC is therefore DMC=6, in which no examination was carriedout so far.

These conditions must be examined at the beginning of each cycle B, andthe next cycle A can only be started, when the address generator DMC hasbeen set to a subsequent stable state. In the appratus shown in FIG. 1the examination in the cycles B can be made as follows:

At the end of the cycle A preceding this cycle B the memory addressingcircuit MEC was set to the next free memory address, i.e. to MEC=6. Upto this time the first counter CNT1 was stepped together with the memoryaddressing circuit MEC (in the cycle A), and it has a value "6". At thebeginning of the cycle B the stepping of the first counter CNT 1 isfinished and the memory addressing circuit MEC will be set by the secondcounter CNT 2 which is stepped one by one from a zero position. In thatcase the address generator DMC has a value which is by one higher thanthat taken at the end of the previous cycle A, i.e. it is now DMC=3.During stepping the memory address from zero, the memory content is readin each memory address and the DATA field is compared to the DMC=3value. The comparison is made by the first comparator KOM 1 whichwatches the DMC=DATA condition only. If the comparator KOM 1 does notindicate such an identity, then the examination will be continued on thenext memory address. From the table of FIG. 3 it can be seen that in theexample in the address of MEC=2 the DATA field has a value of DATA=3which is the same as the actual DMC value. This identity is detected bythe first comparator KOM 1, and in response to the identity conditionthe following events take place:

the address generator DMC steps forward by one step, and

the second counter CNT 2 returns to zero setting again. The examinationof DMC=DATA will be repeated with each memory address. In the examplethe DMC=4 will be found in the address of MEC=4 and the DMC=5 will befound in the address MEC=5.

This process can be repeated until the next free memory address set inthe end of the preceding cycle is reached. This address is stored in theblocked first counter CNT 1. The second comparator KOM 2 is adjusted towatch the identity CNT 1=CNT 2, and if this condition is true, then theactual memory address is equal to that set in the end of the precedingcycle A, in the exemplary case this is 6. This condition indicates theend of the cycle B.

By the alternative use of the cycles A and B the following advantagesare obtained:

(a) the utilization of the memory MEM will be at optimum;

(b) in each group of terminals which are internally interconnected theterminal numbers are stored in subsequent memory addresses, and thefirst member of each group is always stored in a memory address thatfollows an address in which the value of the closing bit is "0", and thegroup terminates in the next address in which the closing bit is again"0";

(c) each "0" value in the closing bit indicates that the terminal storedin the corresponding DATA field is not connected to any other terminalwith higher serial number;

(d) the time required for the examination will be at minimum;

(e) when the "n" memory cells are filled with data, this means that theinternal structure of interconnections of the network NW is alreadyrecorded in the memory MEM, i.e. the examination has finished.

The above described logical system can easily be written in analgorythmical form, and the system can be implemented by hardward meansas shown in FIG. 1, and the logical design of the control unit CU is anobvious consequence of the conditions set out hereinabove. The controlunit CU can be realized either by sequential logical circuits or bymeans of processor operations.

In the control mode it is required that the internal interconnectionsystem of the network NW be already known and stored in the memory. Thecontrol includes the checking of an actual network NW connected to theapparatus according to the invention whether the internal structure ofinterconnections thereof is in full correspondence with that stored inthe memory. If discrepancy is detected, both the numbers of theconcerned terminals and the character of the fault (break orshort-circuit) should be indicated.

This task can be carried out also by the apparatus shown in FIG. 1 asfollows:

When the network NW has been connected to the apparatus the contents ofeach cell of the memory MEM is read out, and the read values of the DATAfields will set the address generators DMC and MPC. In that case theselector SEL is in the second position, in which the data output line 14of the memory MEM is coupled to the data input 12 of the addressgenerator MPC.

The control mode will be described on the basis of the table shown inFIG. 3. When the 0-th memory address (MEC=0) is read, the content of thecell is: DATA=0, Z=0. The number 0 is read in the address generator DMC.The demultiplexer DMPX switches a ground potential to the 0-th terminal.A significant factor in the control operations is the value of theclosing bit Z. In the present case Z=0 which indicates that the 0-thterminal is not connected with any other terminal. From this it followsthat the further checking operations can include short-circuit tests,i.e. the examination whether the ground potential switched on the 0-thterminal occurs due to an unwanted short-circuit on any furtherterminals.

In accordance with this principle in the short-circuit testing cycle thecontrol unit CU does not forward any write enable signal to the addressgenerator DMC which will keep its position. The memory addressingcircuit MEC will now be stepped until the position n is reached, and ineach step the content of the addressed memory cell is read. Since thememory content sets the position of the address generator MPC,practically together with the reading operations the multiplexer MPX isset to the terminals defined by the memory content. In principle, ineach of these steps there is the possibility of examining the logicalvalue of the output V, but such examination would surely includeredundant operations, since if an internally interconnected group ofterminals gets short-circuited, then the short-circuit condition occursin each concerned terminal separately, and the separate identificationsof these short-circuits are unnecessary and they can render the faultlocation difficult. From that reason in the short-circuit testing cyclesthe value of the closing bit Z is watched in all memory readingoperations, and the logical value of the output V is checked only if thevalue of the closing bit is Z=0, which means that the correspondingterminal is the last one of an internally interconnected group ofterminals. In the table of FIG. 3 (in which the column DMC can not beinterpreted in control mode) therefore in the third and fourth memoryaddresses (DATA=MPC=2 and DATA=MPC=4 positions) no checking is carriedout, and the output V is checked only in the position DATA=MPC=5 readout in the address MEC=5. If the logical value of the output V is 0,then the stepping of the memory addressing circuit MEC is continued tillthe last n-th address. If the checked value is found to be "1", then anerror indication is made, and the control unit CU supplies the actualvalues of the address generators DMC and MPC, respectively to a printernot shown in the drawing, which prints the numbers of theshort-circuited terminals.

When the short-circuit testing cycle is finished, the writing of theaddress generator DMC will be enabled and the next memory address MEC=1is set. Whether the next cycle will be a further short-circuit test or acontinuity test is decided by the value of the closing bit Z. If theclosing bit is again zero (Z=0), then a further short-circuit test cycleis made according to the logical conditions set out above. In theexample, however, in the address of MEC=1 Z=1 is read, which means thatthe terminal stored in the first address is connected to at least oneother terminal. The task of the control operation lies in testing thecontinuity of this connection. In case of continuity test always twoadjacent memory addresses are read. The content of the DATA field in thefirst address sets the address generator DMC and the content read in thesecond address sets the address generator MPC. In the example in theaddress MEC=1 DMC=1 is set, and the number 3 read out in the nextaddress MEC=2 is used to set the address generator MPC to the position3. In FIG. 2 it can be seen that the continuity test is justifiedbecause between the actually tested terminals (terminals 1 and 3) theremust be a connection. If during the test the value of the output V is"1", then the continuity is correct and there is no need for an errorindication. Thereafter the address generatord DMC and MPC should be setto the numbers read out in the next memory addresses, i.e. to DMC=3 readout in MEC=2 and to MPC=2 in case of MEC=3. The test will be again ashort-circut test, because in the address of MEC=2 the closing bit isZ=0.

In the following addresses continuity tests are made again. Thecontinuity tests of the interconnected terminals 2, 4 and 5 (made bymeans of the adjustment of the address generators DMC and MPC to thedata stored in directly adjacent memory addresses) will include thefollowing measurements:

(a) MEC=3 DMC=2; MEC=4 MPC=4 measurement between the terminals 2 and 4;

(b) MEC=4 DMC=4; MEC=5 MPC=5 measurement between the terminals 4 and 5.

When the following step is made, i.e. when: MEC=5 DMC=5; MEC=6 MPC=6,then the closing bit is Z=0 in the address of MEC=5 and a short-circuittest will be made.

The control mode consisting of the short-circuit and continuity testcycles is preferable because it does not include any redundantexamination, it delivers the numbers of the erroneously connectedterminals, the type of the fault and it is quick and simple. Especiallyin the control of a network NW which has a high number of terminals, itis possible to carry out the control between predetermined memoryaddresses only, e.g. if an intervention is made in the network in agiven area or if a predetermined interconnection is of highsignificance. To carry out such a limited control the first and lastrequired addresses of the memory addressing circuit MEC should only beadjusted, which can be made by means of appropriate registers or byprocessor operations.

We claim:
 1. A method for the examination of an internal interconnectionsystem between n terminals of an electrical network and for storing theresults in a memory comprising n memory cells by means of sensing theexistence or absence of the signal passage between the terminals,comprising the steps of switching a marking state on the respectiveterminals by means of a demultiplexer (DMPX) with n outputs controlledby an address generator (DMC), and searching the passage of the markingstate by a multiplexer (MPX) with n inputs connected to the terminalsand being set by another address generator (MPC), and in each stablestate of the demultiplexer (DMPX) the pass-through of the marking stateis searched according to the steps of a first cycle designated as cycleA, in each step of said cycle A said multiplexer (MPX) is stepped fromthe terminal associated with said stable state of the demultiplexer(DMPX) until the last terminal thereof and, in each step observing thestate of the multiplexer output and if in said output an active staterepresenting the pass-through of said marking state is detected, theactual address of the multiplexer (MPX) is temporarily stored and, whenthe next active state in said output is detected, the temporarily storedaddress is written in the momentarily addressed cell of the memorytogether with a closing bit having a first logical value associated withsaid active state, whereafter the next address of the memory is set andthe momentary multiplexer address is stored temporarily, and thissequence of steps is continued until the multiplexer (MPX) is connectedto the n-th, last terminal, and in the next step the temporarily storedaddress is written in the momentarily addressed cell of the memorytogether with a closing bit having a first logical value associated withsaid active state, whereafter the next address of the memory is set andthe momentary multiplexer address is stored temporarily, and thissequence of steps is continued until the multiplexer (MPX) is connectedto the n-th, last terminal, and in the next step the temporarily storedaddress is written in the next free address of the memory (MEM) togetherwith a closing bit having a second logical value inverted relative tosaid first logical value, and stepping the memory (MEM) to the nextaddress, then starting a second B-type cycle for adjusting the nextstable state of the demultiplexer (DMPX), in which the demultiplexeraddress is increased by respective steps and in each step this addressis compared with the contents of the already filled memory cells and ifidentity is found, the demultiplexer address is increased by a step and,said increased step is compared to the content of the already writtenmemory cells beginning with the first cell, and if the contents of thefilled memory cells is found not to coincide with the actualdemultiplexer address, then said actual address is accepted as a stabledemultiplexer address, then a further cycle A is started, and by meansof the alternating series of the cycles A and B all the n cells of thememory (MEM) are written in.
 2. The method as claimed in claim 1, inwhich the logical valve of said closing bit is defined as "1" if themultiplexer output (V) is found to be active, and said logical value isdefined as "0" in the step following the examination of the n-thterminal.
 3. A method for testing the identity of an internalinterconnection system interpreted among terminals of a network withthat of a standard network, in which the internal interconnection of thestandard network is recorded in a memory according to claim 1 comprisingthe steps of switching a marking state on the respective terminals ofthe network under test by means of a demultiplexer (DMPX) addressed byan address generator (DMC), and by means of a multiplexer (MPX) withinputs connected to said terminals and addressed by a second addressgenerator (MPC), the arrival of the marking state to the multiplexeroutput is tested as a proof of short-circuit or as a continuity testbetween the actually connected terminals, wherein the short circuit andcontunuity test examinations are carried out in alternating cycles, inthe short circuit control cycles the demultiplexer (DMPX) is set toaddresses for which is true that in the memory cell with the sameaddress the value of the closing bit corresponds to said second logicalvalue, and during maintaining such demultiplexer states the memoryaddress is increased by steps and, in each step the memory content isread and when the read value of the closing bit corresponds to saidsecond logical value, then the muliplexer (MPX) is set to the addressstored in the same memory cell and the output state thereof is examined,and if in said output the marking state corresponding to a short-circuitis detected, then an error indication is made, following the end of eachstep of said cycle the memory cell with the next address is read and thedemultiplexer (DMPX) is set to the position corresponding to the numberstored in said cell, and if the value of the closing bit stored in saidcell has the second logical value, then another short-circuit test cycleis started, and if the closing bit has the first logical value, then asecond type continuity test cycle is started, in said second type themultiplexer (MPX) is set to the position determined by the number storedin the memory cell with the next address, and the state of themultiplexer output is detected, and if an absence of a marking state,said marking state defining a continuity, is measured, an errorindication is made, and if continuity is detected, then thedemultiplexer (DMPX) is set to the position defined by the number storedin the memory cell with said next address and, depending on the value ofthe closing bit stored in said cell a further short-circuit orcontinuity test cycle is started.
 4. The method as claimed in claimed 3,wherein during each error indication, the actual positions of thedemultiplexer (DMPX) and of the multiplexer (MPX) are recorded.
 5. Themethod as claimed in claim 3 wherein said tests are carried out in arange defined between two predetermined limit memory addresses, in whichthe demultiplexer (DMPX) is set first to the position stored in one ofsaid limit addresses, and the type of the first cycle is defined by thelogical value of the closing bit in said address.
 6. Apparatus for theexamination of an internal interconnection system between n terminals ofan electrical network comprising a demultiplexer (DMPX) comprisingoutputs connected to the n terminals of the network (NW) under test, amultiplexer (MPX) comprising inputs connected to said terminals, a firstaddress generator (DMC) connected to address input of the demultiplexer(DMPX), a second address generator (MPC) connected to address input ofthe multiplexer (MPX), a register (REG) connected to the output of themultiplexer (MPX) for temporarily storing the value of said output, aselector (SEL) settable according to the required mode of operation andcomprising an output connected to the address input of the secondaddress generator (MPC), a first input connected to the output of thefirst address generator (DMC), a memory (MEM) comprising n cell whichhas data inputs connected with one exception to the outputs of theregister (REG), the data output of the memory (MEM) are connected withone exception to the address input of the first address generator (DMC)and a second input of the selector (SEL), a memory addressing circuit(MEC) coupled to the address input of the memory (MEM), a means fordetermining the identity of the memory content and the actual positionof the first address generator (DMC), a means for temporary storage ofgiven states of the memory addressing circuit (MEC) and for indicatingwhen the memory addressing circuit (MEC) takes said states again, and acontrol unit (CU) receiving the output of the multiplexer (MPX), theremaining one data output of the memory (MEM), the output of the meansfor determining the identity and the output of the temporary storagemeans, said control unit (CU) comprises control outputs for setting theremaining one data input of the memory (MEM) and for controlling thefirst and second address generators (DMC, MPC), the selector (SEL), theregister (REG), the memory addressing circuitry (MEC) and the memory(MEM).
 7. The apparatus as claimed in claim 6, wherein said means fordetermining the identity comprises a first comparator (KCM 1) having afirst input connected to the output of the first address generator (DMC)and a second input connected to the data output of the memory (MEM). 8.The apparatus as claimed in claim 6, wherein said temporary storagemeans comprises first and second counters (CNT 1, CNT 2) controlled bythe control unit (CU), one of said counters is connected to a settinginput of the memory addressing circuit (MEC), and comprises a secondcomparator (KOM 2) with inputs connected to output of the first andsecond counters (CNT 1, CNT 2).